Microprogram control system

ABSTRACT

According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed. In an instructs a field for controlling the first stage of pipeline is separated from the fields for controlling the other stages and it is read at the same timing as that for reading the fields for controlling the second and successive stages of the flow just prior to the current flow. As a result, the first state of pipeline in the second and successive flow is controlled by microprogram control.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Applications having Ser. Nos.755,321, 758,665 and 752,190.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a microprogram control system, andparticularly to a microprogram control system in a data processing unitemploying a pipeline control system, wherein flexibility is imparted tothe system by reading microinstructions and suppressing a hardwarecontrol mode to execute processings with microinstructions correspondingto each flow when executing an instruction which results in processingseveral flows.

2. Description of the Related Art

As shown in FIG. 1, for example, prefetched instructions are executed ineach stages D, A, T, B, E and W by a pipeline processor. In FIG. 1, 1 isan instruction word register for an instruction word. 2 is a controlstorage or memory storing microinstructions. 3 to 7 are microinstructionfield registers which issue instructions for processing to the hardwarecorresponding to stages D to W. 8 is a general purpose register group. 9is a base register. 10 is an index register. 11 is a displacementregister. 12 is an address calculator or three input adder. 13 is alogical address register. 14 is a TLB (Address Translation Buffer). 15is an address buffer. 16 is a buffer memory. 17 is an operand register.18 to 20 are operand buffer registers. 21 is an operand register. 22 isan operation unit such as an adder. 23 is a result register. The generalpurpose register group 8 is a register group to be used in the threestages D, B and W.

When an instruction 1 is supplied to the pipeline indicated in FIG. 1, amicroinstruction required for executing the pertinent instruction 1 isread and loaded into the register 3 in stage D (decode). Simultaneously,a value is loaded into the registers 9, 10 and 11 to calculate theaddress for the operand (Opr 2 in the figure) which is required forexecuting the pertinent instruction 1. The address of the operand Opr 2is calculated by the calculator 12 in stage A (address) and the resultis loaded into the logical address register 13. The TLB 14 and buffermemory 16 are indexed through the stages T (translate) and B (bufferaccess) and a value of the operand is loaded into the register 17. Atthis time, a value of operand Opr 1 is also loaded into the register 21.At this point, the specified operation is carried out by operation unit22 in the stage E (execution) and the operation result is loaded intothe general purpose register 8 in the stage W (write).

The pipeline control is conducted as explained above and the processingsfor each stage advances in such a way that the microinstructions areread from the control memory 2 shown in the figure and theseinstructions are executed sequentially. On the one hand, when ofexecuting a given instruction 1, the necessary processings are sometimesnot completed by only the processing flow executed along the pipelineprocessing stages from stage D to stage W in FIG. 1 (called theprocessing flow). In general, a plurality of processing flows arerequired for execution of some instructions and the respectiveprocessing flows are desired to be completely executed bymicroinstructions. In such a case, the bit groups of microinstructionscorresponding to one flow of processing read from the control memory 2are forced to correspond to the controls for respective stages of thepipeline and thereby the respective corresponding bit groups instructthe processing in respective stages from the registers 3, 4, 5, 6, 7shown in FIG. 1.

As explained above, instructions have been developed for a plurality offlows and processing has been conducted by reading microinstructionscorresponding to respective flows from the control memory 2. But, thereis a restriction in the time (a minimum available or necessary) foraccessing the control memory 2 and as a result the controls in stage Dof each flow has been performed by hardware and it has been difficult toemploy a control method using microprograms.

Accordingly, the hardware is large in size and when modifications offunctions at stage D are required, the hardware must be modified.Thereby, although it is a data processing unit executing on the basis ofmicroprogram control system, it does not have sufficient flexibility inthe microprogram control for the modification of functions. Therefore, asystem which can realize the microprogram control in all stages isdesired.

Namely, the microprogram control system of the prior art which controlsa data processing unit for pipeline processing takes a longer time forreading control memory and delay for timing for control of the firststage (stage D) of pipeline are necessary. As a result, this stage hasbeen controlled by a hardware decoder or a dummy cycle has been insertedin the cycle clock in order to provide sufficient time to read thecontrol memory.

The control using hardware, however, has a disadvantage in that it isdifficult to realize flexible and sophisticated control and the methodof inserting the dummy cycle is also followed by a disadvantage in thatthe dummy cycle appears between the processing times for theinstructions, thereby lowering processing speed.

SUMMARY OF THE INVENTION

Considering the abovementioned disadvantages of the prior art, it is anobject of the present invention to provide a system for controlling thefirst stage of pipeline using microprograms.

According to the present invention, this object can be attained byproviding a method where the microinstructions are divided into a partfor controlling said first stage D of pipeline and a part forcontrolling the second and successive stages (A˜W). The part forcontrolling the first stage is read simultaneously with the part forcontrolling the stages after the first stage of the first flow justearlier than the current or second flow. The method of the presentinvention provides an advantage in that the first stage of the pipelinecan be controlled by a microprogram and a data processing unit whichexecutes with a more flexible pipeline processing method than that ofprior art can be constructed. In the instruction a field for controllingthe first stage of the pipeline is separated from the fields forcontrolling the other stages and the first stage field is read at thesame timing as that for reading the fields for controlling the secondand successive stages of the flow just prior to the second flow.Thereby, the first stage of the pipeline in second and succeeding flowsis controlled by the microprograms.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the structure of a pipeline for executing instructionsduring the advancement of processing through stages.

FIG. 2 shows the concept of control according to the present invention.

FIGS. 3(A) and 3(B) are logical structures of an embodiment of controlmemory to which the present invention is applied.

FIG. 4 is a block diagram of an embodiment of the present invention.

FIG. 5 is a block diagram of another embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Even when the present invention is applied, stage D of the first flow iscontrolled for execution of the multiflow instruction 1 by hardwarebecause there is insufficient time for reading the control memory 2.

In stage D, microinstructions are read simultaneously by the partcorresponding to the first flow of the control memories for stage A andsuccessive stages (hereinafter referred to as FCS) and by the controlmemory for stage D (hereinafter referred to as NDCS) and themicroinstructions read from FCS are used for controlling stage A andsuccessive stages of the first flow and the microinstructions read fromNDCS are used for controlling stage D of the second flow.

In stage D of the second flow, the microinstructions to be used forcontrolling stage A and successive stages of the second flow are read bya part corresponding to the second flow and successive flows of thecontrol memories for stage A and successive stages (hereinafter referredto as MCS) and simultaneously the microinstructions to be used forcontrol of stage D of the third flow are read from said NDCS.

An inter-relationship between the logical arrangement of controlmemories to which access is made as explained above and the fields areread at the indicated timing as shown in FIG. 3(A). In this figure, D,A, T, . . . indicate the positions of fields for controlling each stagein the microinstruction. The part indicated by X indicates there is nocorresponding part in the NDCS because the stage D of the first flow iscontrolled the hardware. As is apparent from FIG. 3(A), even when thefield for controlling stage D which forms the microinstructionscorresponding to the first flow and the fields for controlling stages A,T, . . . , are separated for NDCS and MCS, access can be realized usingthe same address. However, with respect to the read timing, as shown inFIG. 3(B), in the stage D of the first flow, field 24 corresponding tocontrol for the first flow and field 25 corresponding to control ofstage D for the second flow are read at the same timing. In stage D ofthe second flow shown in FIG. 2, field 26 corresponding to control forstage A and successive stages for the second flow and field 27corresponding to control of stage D for the third flow are read at thesame timing. The similar processings are repeated for successive stages.

FIG. 4 is a profile explained by referring to FIG. 3. FIG. 4 shows ablock diagram of an embodiment for making access to the control memories2 shown in FIG. 1. In the same figure, 32 is a selector; 33 is a controlmemory for stage D (NDCS); 34 is a part corresponding to the first flowof the control memories for stage A and successive stages (FCS); 35 is apart corresponding to the second flow and successive flows of thecontrol memories for stage A and successive memories; 36 and 37 aremicroprogram instruction decoders; 38 is a latch; 39 to 41 are gates. 43is a decoder for cycle D of the first flow and 44 is a circuit forgenerating control memory addresses for the second and successive flows.

A method of making access to the control memories in the presentinvention is explained hereunder by referring to FIGS. 2, 3 and 4. Whenan instruction to be executed is loaded into the instruction register 1,access is made to FCS 34 by the operation code at the timing of stage Dof the first flow of said instruction and thereby the fields ofmicroinstruction to be used for control of stage A and successive stagesof the first flow are read. Simultaneously access is also made to NDCS33 through the selector 32, and thereby the fields of themicroinstruction to be used for control of stage D of the second floware read and the control signals to be used for control in each stageare output by the decoders 36, 37.

The addresses used for the access are stored in latch 38, access is alsomade to MCS 35 at the timing of stage D of the second flow 2. Thus, thefields of microinstruction used for the control of stage A andsuccessive stages of the second flow are read out. Simultaneously,access is made to the NDCS 33 through the selector 32 with the nextmicroaddress generated by the address generating circuit 44 on the basisof the address part of microinstruction to be used for the control ofstage A and successive stages of the first flow which has been read anddecoded previously. Thereby, the fields of the microinstruction to beused for the control of stage D of the next or third flow, is read outusing the microaddress. The address is stored in the latch 38 and accessis made to MCS 35 in the stage D for the next field in the third flow.

Thereafter, in a similar manner, access is made to control memory (MCS)35 for stage A and successive stages of the flow with the address storedin the latch 38 in stage D of each flow in order to read the field ofthe microinstruction to be used for the control of stage A andsuccessive stages. Simultaneously, access is made to control memory(NDCS) 33 for stage D of the next flow with an output of the addressgenerating circuit to read the field of the microinstruction to be usedfor the control of the stage and is followed by repetition of storing ofthe address in the latch 38.

With the above operation, a control system using a microprogram can beintroduced into the first stage D of the pipeline which has beenpreviously controlled by hardware.

It is desirable to employ the above described structure in FIG. 4,however, further improvements can be made. When processing is executedusing plural flows as explained above, the processing contents of thefirst flow is different from that of the second flow and the number ofcontrol points or lines in the first flow can be lower than the numberof control points in the second and successive flows. In FIG. 4, the bitwidth of content stored in the FCS is equal to the bit width of contentstored in the MCS, without consideration of such the different incontrol points. Particularly, in a current large scale data processingunit, a majority of the generally used instructions are processed withinthe first flow. Therefore, it is desirable to effectively use thedifference between the microinstruction corresponding to said first flowand the microinstruction corresponding to the second flow.

FIG. 5 shows a block diagram of an embodiment of the present inventionwhich improves in the above area. In the same figure Numerals, 32 to 41correspond to the same element as those in FIG. 4 and 42 is a decoderfor FCS. The operation of FIG. 5 is the same as that in FIG. 4. However,the bit width of FCS 34 shown in FIG. 5 is smaller than that of MCS 35and the control memory in FIG. 5 is more effectively used as comparedwith FIG. 4 and the access time is reduced due to the reduction in thebit width and address range.

We claim:
 1. A microprogram control method for a multi-flow machineinstruction executed by several microinstructions, each microinstructionhaving plural parts, using a pipeline having a plurality of executionstages each microinstruction part controlling a different stage, andeach flow controlled by a different microinstruction, said methodcomprising the steps of:hardware decoding the machine instruction forcontrolling a first stage of a first flow in said pipeline, fetching asecond part of a first microinstruction for controlling second andsuccessive stages in the first flow and fetching a first part of asecond microinstruction for controlling a first stage in a second flow,respectively in parallel; and executing the second part of the firstmicroinstruction, executing the first part of the secondmicroinstruction and fetching a second part of the secondmicroinstruction for controlling the second and successive stages of thesecond flow, respectively in parallel.
 2. A microprogram control methodaccording to claim 1, further comprising:using a first memory forstoring said first part of said second microinstruction and a secondmemory for storing said second part of said first and secondmicroinstructions; delaying address information for accessing said firstmemory by at least one stage and accessing said second memory in saidsecond flow; and accessing said first memory and said second memory inparallel in the second flow.
 3. A microprogram control method accordingto claim 2, further including:using the second memory including a firstflow memory which stores microinstructions for processing of the firstflow and a second flow memory which stores microinstructions forprocessing of the second and successive flows; and usingmicroinstructions stored in the first and second flow memories with adifferent bit width.
 4. A microprogram control method according to claim1, wherein the processing which controls the first stage correspondingto the first flow among the processings developed in said multiple flowsis executed using hardware control.
 5. A method of processing amulti-flow machine instruction, having first and second flows whereexecution of each flow is controlled by a different microinstruction, ina pipeline processing unit having a hardware decoder, a microprogramcontrolled control storage access stage and microprogram controlledsuccessive stages, each microinstruction having plural parts each partcontrolling one of the stages, the microinstructions being shiftedthrough the successive stages, said method comprising the steps of:(a)decoding the machine instruction for the first stage of the first flowusing the hardware decoder; (b) first fetching and second using a firstflow microinstruction for controlling the microprogram controlledsuccessive stages of the first flow and simultaneously, with said firstfetching, fetching a decode control storage access stagemicroinstruction for the second flow; and (c) executing the access stagemicroinstruction of the second flow using the microprogram controlledcontrol storage access stage and simultaneously, with the executing,fetching a second flow microinstruction for controlling the microprogramcontrolled successive stages of the second flow and then executing thefetched second flow microinstruction for controlling the successivestages of the second flow.
 6. A pipeline processing unit control systemhaving a decoding stage and successive stages, said system comprising:aninstruction register for storing a multi-flow machine instruction havingfirst and second flows where execution of each flow is controlled by adifferent microinstruction and each microinstruction having plural partseach part controlling one of the stages; a hardware decoder, connectedto said instruction register, for decoding the multi-flow machineinstruction for the first flow in the decoding stage; a firstmicroprogram memory, connected to said instruction register, for storingmicroinstructions for the successive stages of the first and secondflows; a second microprogram memory, connected to said instructionregister, for storing microinstructions for a control storage accessstage of the second flow; and microprogram decoder means, connected tosaid first and second microprogram memories, for decoding themicroinstructions in the access stage of the second flow and insuccessive stages in the second flow.
 7. A system as recited in claim 6,further comprising:a latch, connected between said instruction registerand said first microprogram memory, for storing an address of themicroinstructions in the successive stages of the first and secondflows; and an address generating circuit, connected to said decodermeans and said latch, for generating an address for themicroinstructions of the second flow.
 8. A pipeline processing unitcontrol system having a decoding stage and successive stages, saidsystem comprising:an instruction register for storing a multi-flowinstruction having first and second flows where execution of each flowis controlled by a different microinstruction, each microinstructionhaving plural parts each part controlling one of the stages; a hardwaredecoder, connected to said instruction lregister, for decoding themulti-flow machine instruction for the first flow in the decoding stage;a first microprogram memory, connected to said instruction register, forstoring microinstructions for the successive stages of the first flow; asecond microprogram memory, connected to said instruction register, forstoring microinstructions for a control store access stage of the secondflow; a third microprogram memory, connected to said instructionregister, for storing microinstructions for the successive stages of thesecond flow; and microprogram decoder means, connected to said firstthrough third microprogram memories, for decoding the microinstructions.9. A system as recited in claim 8, further comprising:a selectorconnected to said instruction register and said second microprogrammemory; a latch, connected between said selector and said thirdmicroprogram memory, for storing an address of the microinstructions inthe successive stages of the first and second flows; and an addressgenerating circuit, connected to said decoder means and said selector,for generating an address for the microinstructions of the second flow.10. A method according to claim 1, wherein said pipeline includesmicroinstruction stage registers corresponding to the pipeline stagesand said method includes shifting the microinstructions through thestage registers and controlling the corresponding pipeline stage usingoutputs of the corresponding stage register.
 11. A method according toclaim 5, wherein said pipeline includes microinstruction stage registerscorresponding to pipeline stages and said method includes shifting themicroinstructions through the stage registers and controlling thecorresponding pipeline stage using outputs of the corresponding stageregister.
 12. A control system according to claim 6, the pipeline havingpipeline execution stages and said control system further comprisingseries connected microinstruction stage registers corresponding to thepipeline execution stages and connected to said first program memory,each register corresponding to a stage, the microinstructions beingshifted successively through said stage registers during the first andsecond flows.
 13. A control system according to claim 8, the pipelinehaving pipeline execution stages and said control system furthercomprising series connected microinstruction stage registerscorresponding to the pipeline execution stages, and connected to saidfirst program memory, each register corresponding to a stage, themicroinstructions being shifted successively through said stageregisters during the first and second flows.